samsung exynos 4412 芯片数据手册 -澳门皇冠贵宾会网址

exynos 是韩国三星电子所发展的处理器代号。
exynos源自希腊文字exypnos，意思是智慧。三星的galaxy s ii就是使用自家的exynos 4210处理器。

2011年9月三星发布一款双核处理器exynos 4212，采用arm cortex-a9架构，主频为1.5ghz。2011年12月三星发表全新exynos 5250微处理器，32nm制程技术，运作时脉高达2ghz，未来主要将应用在平板装置。

exynos soc 列表

型号	半导体技术	cpu 指令集	cpu	gpu	内存技术	可达性	应用装置
exynos 3 single （内部编号：exynos 3110 ；旧称：s5pc110 / hummingbird）	45 nm	armv7	1 ghz单核arm cortex-a8	200 mhzpowervrsgx540	lpddr1, lpddr2, or ddr2	2010	samsung galaxy s line、samsung gt-s8500 wave、samsung wave ii s8530、nexus s、魅族 m9、samsung galaxy tab、samsung droid charge、exhibit 4g、samsung infuse
exynos 4 dual 45nm （内部编号：exynos 4210 ）	45 nm	armv7	1.2-1.4 ghz双核arm cortex-a9	arm mali-400 mp4	lpddr2, ddr2 or ddr3	2011	samsung galaxy s ii、samsung galaxy note、samsung galaxy tab 7.7、hardkernel odroid-a、魅族 mx、cotton candy by fxi tech
exynos 4 dual 32nm （内部编号：exynos 4212 ）	32 nm	armv7	1.5 ghz双核arm cortex-a9	arm mali-400 mp4	lpddr2, ddr2 or ddr3	2011	魅族mx 双核升级版
exynos 4 quad （内部编号：exynos 4412 ）	32 nm	armv7	1.4-1.6 ghz四核arm cortex-a9	440 mhz armmali-400mp4	lpddr2, ddr2 or ddr3	2012	samsung galaxy s iii、魅族mx四核、魅族mx2[6]、samsung galaxy note 10.1、samsung galaxy note ii（mali-400 mp4 @ 533 mhz)、联想 k860、samsung galaxy note 8
exynos 5 dua （内部编号：exynos 5250 ）	32 nm	armv7	1.7-2.0 ghz双核arm cortex-a15 mpcore	arm mali-t604		2012	chromebook、nexus 10
exynos 5 octa （内部编号：exynos 5410 ）	28 nm	armv7	1.6-1.8 ghz四核arm cortex-a15 mpcore 1.2 ghz四核arm cortex-a7 (arm big.little)	powervr sgx 544mp3		2013	samsung galaxy s iv国际版
exynos 5450	28 nm	armv7	1.7-2.0 ghz四核arm cortex-a15 mpcore	arm mali-t658[来源请求]		2013

文档目录

1 product overview ................................................................................. 1-1
1.1 introduction ............................................................................................................................................. 1-1
1.2 features .................................................................................................................................................. 1-2
1.2.1 multi-core processing unit ............................................................................................................... 1-4
1.2.2 memory subsystem .......................................................................................................................... 1-5
1.2.3 multimedia ....................................................................................................................................... 1-6
1.2.4 audio subsystem .............................................................................................................................. 1-8
1.2.5 image signal processing subsystem ............................................................................................... 1-8
1.2.6 connectivity ..................................................................................................................................... 1-9
1.2.7 system peripheral .......................................................................................................................... 1-11
1.3 conventions .......................................................................................................................................... 1-13
1.3.1 register rw conventions .............................................................................................................. 1-13
1.3.2 register value conventions ........................................................................................................... 1-13
2 memory map .............................................................................................. 2-1
2.1 overview ................................................................................................................................................. 2-1
2.2 sfr base address ................................................................................................................................. 2-2
3 chip id .......................................................................................................... 3-1
3.1 overview ................................................................................................................................................. 3-1
3.2 register description ................................................................................................................................ 3-2
3.2.1 register map summary .................................................................................................................... 3-2
4 general purpose input/output (gpio) control ......................... 4-1
4.1 overview ................................................................................................................................................. 4-1
4.2 features .................................................................................................................................................. 4-3
4.2.1 input/output description ................................................................................................................... 4-3
4.3 register description ................................................................................................................................ 4-5
4.3.1 registers summary .......................................................................................................................... 4-5
4.3.2 part 1 ............................................................................................................................................. 4-20
4.3.3 part 2 ........................................................................................................................................... 4-124
4.3.4 part 3 ........................................................................................................................................... 4-289
4.3.5 part 4 ........................................................................................................................................... 4-298
5 clock management unit ...................................................................... 5-1
5.1 overview ................................................................................................................................................. 5-1
5.2 clock domains ........................................................................................................................................ 5-1
5.3 clock declaration .................................................................................................................................... 5-3
5.3.1 clocks from clock pads ................................................................................................................... 5-3
5.3.2 clocks from cmu .............................................................................................................................. 5-4
5.4 clock relationship .................................................................................................................................. 5-5
5.4.1 recommended pll pms value for apll and mpll ...................................................................... 5-7
5.4.2 recommended pll pms value for epll ........................................................................................ 5-8
5.4.3 recommended pll pms value for vpll ........................................................................................ 5-9
5.5 clock generation .................................................................................................................................. 5-10
5.6 clock configuration procedure .............................................................................................................. 5-15
5.6.1 clock gating .................................................................................................................................. 5-16
5.6.2 clock diving ................................................................................................................................... 5-16
5.7 special clock description ...................................................................................................................... 5-17
5.7.1 special clock table ........................................................................................................................ 5-17
5.8 clkout ................................................................................................................................................ 5-20
5.9 i/o description ...................................................................................................................................... 5-23
5.10 register description ............................................................................................................................. 5-24
5.10.1 register map summary ................................................................................................................ 5-26
6 interrupt controller ......................................................................... 6-1
6.1 overview ................................................................................................................................................. 6-1
6.2 features .................................................................................................................................................. 6-2
6.2.1 security extensions support ............................................................................................................ 6-2
6.2.2 implementation-specific configurable features .............................................................................. 6-3
6.3 interrupt source ...................................................................................................................................... 6-4
6.3.1 interrupt sources connection ........................................................................................................... 6-4
6.3.2 gic interrupt table ........................................................................................................................... 6-5
6.4 functional overview .............................................................................................................................. 6-13
6.5 register description ............................................................................................................................... 6-14
6.5.1 register map summary .................................................................................................................. 6-14
7 interrupt combiner .............................................................................. 7-1
7.1 overview ................................................................................................................................................. 7-1
7.2 features .................................................................................................................................................. 7-1
7.3 functional description ............................................................................................................................. 7-2
7.3.1 block diagram ................................................................................................................................. 7-2
7.4 interrupt sources..................................................................................................................................... 7-3
7.4.1 interrupt combiner ............................................................................................................................ 7-3
7.5 functional description ............................................................................................................................. 7-8
7.6 register description ................................................................................................................................ 7-9
7.6.1 register map summary .................................................................................................................... 7-9
7.6.2 interrupt combiner .......................................................................................................................... 7-10
8 direct memory access controller (dmac) ................................. 8-1
8.1 overview ................................................................................................................................................. 8-1
8.2 features .................................................................................................................................................. 8-2
8.3 register description ................................................................................................................................ 8-5
8.3.1 register map summary .................................................................................................................... 8-5
8.4 instruction .............................................................................................................................................. 8-14
9 srom controller ................................................................................... 9-1
9.1 overview ................................................................................................................................................. 9-1
9.2 features .................................................................................................................................................. 9-1
9.3 block diagram ......................................................................................................................................... 9-1
9.4 functional description ............................................................................................................................. 9-2
9.4.1 nwait pin operation ........................................................................................................................ 9-2
9.4.2 programmable access cycle ........................................................................................................... 9-3
9.5 i/o description ........................................................................................................................................ 9-4
9.6 register description ................................................................................................................................ 9-5
9.6.1 register map summary .................................................................................................................... 9-
10 nand flash controller .................................................................. 10-1
10.1 overview ............................................................................................................................................. 10-1
10.2 features .............................................................................................................................................. 10-1
10.3 functional description ......................................................................................................................... 10-2
10.3.1 block diagram .............................................................................................................................. 10-2
10.3.2 nand flash memory timing ........................................................................................................ 10-3
10.4 software mode .................................................................................................................................... 10-4
10.4.1 data register configuration ......................................................................................................... 10-4
10.4.2 1/4/8/12/16-bit ecc ...................................................................................................................... 10-5
10.4.3 2048 byte 1-bit ecc parity code assignment table ................................................................... 10-6
10.4.4 32 byte 1-bit ecc parity code assignment table ....................................................................... 10-6
10.4.5 1-bit ecc module features .......................................................................................................... 10-6
10.4.6 1-bit ecc programming guide ..................................................................................................... 10-7
10.4.7 4-bit ecc programming guide (encoding) .............................................................................. 10-8
10.4.8 4-bit ecc programming guide (decoding) .............................................................................. 10-9
10.4.9 8/12/16-bit ecc programming guide (encoding) .................................................................. 10-10
10.4.10 8/12/16-bit ecc programming guide (decoding) ................................................................ 10-11
10.4.11 ecc parity conversion code guide for 8/12/16-bit ecc ........................................................ 10-12
10.4.12 lock scheme for data protection ............................................................................................. 10-13
10.5 programming constraints .................................................................................................................. 10-14
10.6 i/o description .................................................................................................................................. 10-14
10.7 register description ........................................................................................................................... 10-15
10.7.1 register map summary .............................................................................................................. 10-15
10.7.2 nand flash interface and 1/4-bit ecc registers ...................................................................... 10-17
10.7.3 ecc registers for 8, 12 and 16-bit ecc .................................................................................... 10-29
11 pulse width modulation timer ..................................................... 11-1
11.1 overview ............................................................................................................................................. 11-1
11.2 features .............................................................................................................................................. 11-4
11.3 pwm operation................................................................................................................................... 11-5
11.3.1 prescaler and divider ................................................................................................................... 11-5
11.3.2 basic timer operation .................................................................................................................. 11-6
11.3.3 auto-reload and double buffering ............................................................................................... 11-8
11.3.4 timer operation example ............................................................................................................. 11-9
11.3.5 initialize timer (setting manual-up data and inverter) .............................................................. 11-10
11.3.6 pwm .......................................................................................................................................... 11-10
11.3.7 during current isr. (interrupt service routine) output level control ...................................... 11-11
11.3.8 dead zone generator ................................................................................................................. 11-12
11.4 i/o description .................................................................................................................................. 11-13
11.5 register description ........................................................................................................................... 11-14
11.5.1 register map summary .............................................................................................................. 11-14
12 watchdog timer .................................................................................. 12-1
12.1 overview ............................................................................................................................................. 12-1
12.2 features .............................................................................................................................................. 12-1
12.3 functional description ......................................................................................................................... 12-2
12.3.1 wdt operation ............................................................................................................................. 12-2
12.3.2 wtdat and wtcnt .................................................................................................................... 12-3
12.3.3 wdt start .................................................................................................................................... 12-3
12.3.4 consideration of debugging environment .................................................................................... 12-3
12.4 register description ............................................................................................................................. 12-4
12.4.1 register map summary ................................................................................................................ 12-4
13 universal asynchronous receiver and transmitter ......... 13-1
13.1 overview ............................................................................................................................................. 13-1
13.2 features .............................................................................................................................................. 13-0
13.3 uart description ............................................................................................................................... 13-1
13.3.1 data transmission ........................................................................................................................ 13-2
13.3.2 data reception ............................................................................................................................. 13-2
13.3.3 afc .............................................................................................................................................. 13-3
13.3.4 example of non afc (controlling nrts and ncts by software) ............................................... 13-4
13.3.5 trigger level of tx/rx fifo and dma burst size in dma mode ................................................ 13-4
13.3.6 rs-232c interface ........................................................................................................................ 13-4
13.3.7 interrupt/dma request generation .............................................................................................. 13-5
13.3.8 uart error status fifo .............................................................................................................. 13-7
13.4 uart input clock description ........................................................................................................... 13-10
13.5 i/o description .................................................................................................................................. 13-11
13.6 register description ........................................................................................................................... 13-12
13.6.1 register map summary .............................................................................................................. 13-12
14 inter-integrated circuit ................................................................. 14-1
14.1 overview ............................................................................................................................................. 14-1
14.2 features .............................................................................................................................................. 14-2
14.3 functional description ......................................................................................................................... 14-2
14.3.1 block diagram .............................................................................................................................. 14-2
14.4 i2c-bus interface operation ................................................................................................................ 14-3
14.4.1 start and stop conditions ............................................................................................................. 14-4
14.4.2 data transfer format ................................................................................................................... 14-5
14.4.3 ack signal transmission ............................................................................................................. 14-6
14.4.4 read-write operation ................................................................................................................... 14-7
14.4.5 bus arbitration procedures ........................................................................................................... 14-7
14.4.6 abort conditions ........................................................................................................................... 14-7
14.4.7 configuring i2c-bus ..................................................................................................................... 14-7
14.4.8 flowcharts of operations in each mode ...................................................................................... 14-8
14.5 i/o description .................................................................................................................................. 14-12
14.6 register description ........................................................................................................................... 14-13
14.6.1 register map summary .............................................................................................................. 14-13
15 serial peripheral interface ......................................................... 15-1
15.1 overview ............................................................................................................................................. 15-1
15.2 features .............................................................................................................................................. 15-1
15.2.1 operation of spi ........................................................................................................................... 15-2
15.3 spi input clock description ................................................................................................................. 15-5
15.4 io description ..................................................................................................................................... 15-6
15.5 register description ............................................................................................................................. 15-7
15.5.1 register map summary ................................................................................................................ 15-7
16 display controller .......................................................................... 16-1
16.1 overview ............................................................................................................................................. 16-1
16.2 features .............................................................................................................................................. 16-2
16.3 functional description ......................................................................................................................... 16-4
16.3.1 brief description ........................................................................................................................... 16-4
16.3.2 data flow ..................................................................................................................................... 16-5
16.3.3 overview of the color data .......................................................................................................... 16-8
16.3.4 palette usage ............................................................................................................................. 16-23
16.3.5 window blending ........................................................................................................................ 16-26
16.3.6 vtime controller operation ....................................................................................................... 16-35
16.3.7 virtual display ............................................................................................................................. 16-39
16.3.8 rgb interface specification ....................................................................................................... 16-40
16.3.9 lcd indirect i80 system interface .............................................................................................. 16-43
16.4 i/o description .................................................................................................................................. 16-47
16.5 register description ........................................................................................................................... 16-48
16.5.1 register map summary .............................................................................................................. 16-49
16.5.2 palette memory ........................................................................................................................... 16-56
16.5.3 control register .......................................................................................................................... 16-57
16.5.4 gamma lookup table .............................................................................................................. 16-131
16.5.5 shadow windows control ........................................................................................................ 16-134
16.5.6 palette ram .............................................................................................................................. 16-136
17 keypad interface ............................................................................... 17-1
17.1 overview ............................................................................................................................................. 17-1
17.2 debouncing filter ................................................................................................................................ 17-3
17.3 filter clock .......................................................................................................................................... 17-3
17.4 wakeup source................................................................................................................................... 17-3
17.5 keypad scanning procedure for software scan ................................................................................. 17-4
17.6 keypad scanning procedure for hardware scan ................................................................................ 17-9
17.7 i/o description .................................................................................................................................. 17-10
17.8 register description ........................................................................................................................... 17-12
17.8.1 register map summary .............................................................................................................. 17-12
18 adc ........................................................................................................... 18-1
18.1 overview ............................................................................................................................................. 18-1
18.2 features .............................................................................................................................................. 18-1
18.3 functional description ......................................................................................................................... 18-1
18.3.1 block diagram .............................................................................................................................. 18-1
18.3.2 adc selection .............................................................................................................................. 18-2
18.3.3 a/d conversion time.................................................................................................................... 18-2
18.3.4 adc conversion mode ................................................................................................................. 18-2
18.3.5 standby mode ............................................................................................................................... 18-3
18.4 adc input clock diagram .................................................................................................................... 18-4
18.5 i/o descriptions................................................................................................................................... 18-5
18.6 register description ............................................................................................................................. 18-6
18.6.1 register map summary ................................................................................................................ 18-6